SPI1 bit mode control register.
SPI_MEM_CACHE_USR_ADDR_4BYTE | For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable. |
SPI_MEM_FDIN_DUAL | For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. |
SPI_MEM_FDOUT_DUAL | For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. |
SPI_MEM_FADDR_DUAL | For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. |
SPI_MEM_FDIN_QUAD | For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. |
SPI_MEM_FDOUT_QUAD | For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. |
SPI_MEM_FADDR_QUAD | For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. |